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Chapter 4

Schematic Design Entry

This chapter contains the following sections:

Refer to the “Top-Level Designs” section of the “Design Methodologies - Schematic Flow” chapter for several examples of top-level schematic designs.

Refer to the “Schematic (EDIF file) in a VHDL or Verilog Design” section of the “Design Methodologies - HDL Flow” chapter for an example of instantiating a schematic macro as a black box into a VHDL or Verilog design.

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