This chapter contains the following sections:
Refer to the Top-Level Designs section of the Design Methodologies - Schematic Flow chapter for several examples of top-level schematic designs.
Refer to the Schematic (EDIF file) in a VHDL or Verilog Design section of the Design Methodologies - HDL Flow chapter for an example of instantiating a schematic macro as a black box into a VHDL or Verilog design.