Simulation/Verification

Simulation and verification tools are available for both Schematic and HDL Flow projects to determine if the timing requirements and functionality of your design have been met.

Logic Simulator

The Logic Simulator is a real-time interactive design tool for both functional and timing simulation of designs. You access the Logic Simulator from the project flowchart when you click the Simulation button or the Timing Simulation icon on the Verification button.

The Logic Simulator creates an electronic breadboard of your design directly from your design's netlist. The breadboard is tested with signals called test vectors. Each test vector lists logical states of all stimulus signals at a selected time interval. See the “Functional Simulation” chapter and the “Verification and Programming” chapter for more information on simulations. For details on how to use the Logic Simulator, select Help Foundation Help Contents Logic Simulator.

Timing Analyzer

Select the Timing Analyzer icon on the Verification button on the project flowchart to access the Timing Analyzer for verification based on the post-layout timing netlist. The Timing Analyzer is used to verify that the delay along a given path or paths meets your specified timing requirements. It creates timing analysis reports that you customize by applying filters. It organizes and displays data that allows you to analyze the critical paths in your circuit, the cycle time of the circuit, the delay along any specified paths, and the paths with the greatest delay. It also provide a quick analysis of the effect of different speed grades on the same design.

Specialized Simulation Controls

Typically, the Simulation and Verification functions are invoked from the project flowchart buttons. You can access the following individual functions from the Project Manager toolbar, if needed.

• Gate Simulator
  
  When you select Tools Simulation/Verification Gate Simulator from the Project Manager toolbar, you access three startup options for the simulator.
  
  
  • Opening the simulator with the netlist from the currently open Foundation project
    
    
  • Selecting the netlist manually
    
    
  • Opening the simulator without loading a netlist
    
    

• Checkpoint Gate Simulation Control
  
  Checkpoint simulation pulls simulation data from the current stage of the design database. If you want to select which netlist (hierarchical or flat NGA netlist) to use for timing simulation, you can access the Checkpoint Gate Simulation Control dialog by selecting Tools Simulation/Verification Checkpoint Gate Simulation Control on the Project Manager toolbar.
  
  

HDL Behavioral Simulation Capabilities

Foundation Series 1.5 provides the option of adding HDL behavioral simulation capabilities to all design flows. Evaluation versions of HDL simulators from Aldec, Incorporated, and from MTI are included with your Xilinx software. Sale and support for Aldec's ACTIVE-VHDL Behavioral Simulator and for MTI's ModelSim product are handled directly by those vendors.