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HDL Designs with Instantiated Xilinx Unified Library Components

It is possible to instantiate certain Xilinx Unified Library components directly into your VHDL or Verilog code. In general, you will find this most useful for components that the Express compiler is unable to infer, such as BSCAN, RAM, and certain types of special Xilinx components. The “Instantiated Components” appendix lists the most commonly instantiated components, including descriptions of their function and pins.

When instantiating Unified Library components, the component must first be declared before the begin keyword in VHDL the architecture and then may be instantiated multiple times in the body of the architecture.

The following example shows how to instantiate the STARTUP component in a VHDL file, which in turn allows use of the dedicated GSR (global set/reset) net.

The following sample written in VHDL shows an example of an instantiated Xilinx Unified Library component, STARTUP.

library IEEE;
use IEEE.std_logic_1164.all;

   entity gsr_test is 
      port ( 
         CLK: in STD_LOGIC;
         D_IN: in STD_LOGIC;
         RESET: in STD_LOGIC;       
         Q_OUT: out STD_LOGIC
      );
   end gsr_test;

   architecture gsr_test_arch of gsr_test is
   component STARTUP
      port (GSR: in std_logic);
   end component;

   begin

   U1: STARTUP  port map (GSR=>RESET);

   process (CLK)
   begin

      if (CLK event and CLK='1') then 
         Q_OUT <= D_IN;
      end if;
   end process;

   end gsr_test_arch;
  1. The HDL code must be added to the project. Select Project Add to Project from the HDL Editor or select Document Add from the Project Manager.

  2. Synthesize the design by selecting the Synthesis button on the Project Manager Flow tab.The synthesizer will automatically include top level input and output pads for the designated top-level design.

    For more information about HDL designs, see the “HDL Design Entry and Synthesis” chapter or, in the HDL Editor window, select Help Help Topics.

  3. To complete the design, refer to the “Synthesizing the Design”through the “Programming the Device” sections under the “All-HDL Designs” section.

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