Synthesis of HDL Modules

Foundation 1.5 projects can be either HDL Flow or Schematic Flow projects. Many of the HDL editing and synthesis operations described in this section are the same for both flows; however, differences do exist and are noted where appropriate.

You can use two different design flow methodologies for Foundation 1.5 projects: Schematic Flow or HDL Flow.

Schematic Flow Methodology

In a Schematic Flow project, VHDL and Verilog modules can only be underlying modules in a top-level schematic design. Each HDL file is synthesized and optimized separately. Top-level ABEL designs and ABEL State Machine designs are only supported in the Schematic Flow.

The Schematic Flow methodology can be beneficial if you have a few HDL blocks in an otherwise schematic environment. In this case, you only synthesize the individual HDL module.

Following is the general procedure to synthesize HDL Modules in Schematic Flow Projects.

1. Open the HDL file in the HDL Editor. This can be done by the methods listed in the “HDL File Selection” section or by double clicking on the .vhd (VHDL) or .v (Verilog) file in the Project Manager.
   
   
2. Select Synthesis Options to access the FPGA Express Options window. In the General tab, select the optimization options for the module.
   
   
   
   
3. Click on the Advanced tab. Select the top-level entity and architecture, and click OK.
   
   
   
   
4. To synthesize the module and create a symbol, choose Project Create Macro from the HDL Editor window.
   
   
5. Repeat step 4 for each HDL module.
   
   For details on conducting a functional simulation, refer to the “Functional Simulation” chapter.
   
   

HDL Flow Methodology

In an HDL Flow project, all VHDL and Verilog files are exported to the synthesis tool and optimized. Pre-Implementation constraint editing, cross-boundary optimization, and auto I/O buffer insertion are only available in an HDL Flow Project.

The HDL Flow approach provides an easier method of compilation. It requires only a single synthesis action for the whole design. In addition, this method includes optional cross-boundary optimization of the entire design, editing of constraints prior to implementation, and auto I/O buffer insertion.

Following is the general procedure to synthesize HDL Modules in HDL Flow Projects.

1. Be sure that all HDL files are added to the project. See the “Adding the File to the Project” section for instructions on adding files to a project.
   
   
2. From the Project Manager window, set the global synthesis options by selecting Synthesis Synthesis Options. Set the Default FSM Encoding style, XNF Bus Style, and Default Frequency. Check the Export Timing Constraint box if you want to have timing and pin location constraints entered after the elaboration step to be automatically exported to place and route tools.
   
   For FSM Encoding style, use the following guidelines for best results.
   
   
   • For FPGAs, choose One Hot.
     
     
   • For CPLDs, choose Binary.
     
     
     
     
3. To synthesize the design, click the Synthesis button on the Flow tab. This accesses the Synthesis/Implementation dialog box.
   
   
   
   
4. In the Synthesis/Implementation dialog box, select the name of the top-level VHDL entity or Verilog module, enter a version name, select the target device, and modify the synthesis settings as desired. Click OK to synthesize the design.