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The functional elements of a Verilog description consist of function declarations, task statements, and always blocks. These elements describe the function of the circuit but do not describe its physical makeup or layout. The choice of gates and components is left entirely to Foundation Express.
You can construct functional descriptions with the Verilog functional constructs described in the “Functional Descriptions” chapter. These constructs can appear within functions or always blocks. Functions imply only combinatorial logic; always blocks can imply either combinatorial or sequential logic.
Although many Verilog functional constructs appear sequential in nature (for example, for loops and multiple assignments to the same variable), these constructs describe combinatorial logic networks. Other functional constructs imply sequential logic networks. Latches and registers are inferred from these constructs. Refer to the “Register and Three-State Inference” chapter.