Mixing Structural and Functional Descriptions

When you use a functional description style in a design, you typically describe the combinatorial portions of a design in Verilog functions, always blocks, and assignments. The complexity of the logic determines whether you use one or many functions.

The example “Mixed Structural and Functional Descriptions” shows how structural and functional description styles are mixed in a design specification. In this example, the function detect_logic determines whether the input bit is a 0 or a 1. After making this determination, detect_logic sets ns to the next state of the machine. An always block infers flip-flops to hold the state information between clock cycles.

You can directly specify elements of a design as module instantiations at the structural level. For example, see the three-state buffer, t1, in the following example of mixed structural and functional descriptions.

Note: The three-state buffers can be inferred. For more information, refer to the “Three-State Inference” section of the “Register and Three-State Inference” chapter.)

You can also use this description style to identify the wires and ports that carry information from one part of the design to another.

// This finite state machine (Mealy type) reads one

// bit per clock cycle and detects three or more

// consecutive ones.

module three_ones(signal,clock,detect,output_enable);

input signal, clock, output_enable;

output detect;

// Declare current state and next state variables.

reg [1:0] cs;

reg [1:0] ns;

wire ungated_detect;

// declare the symbolic names for states

parameter NO_ONES=0,ONE_ONE=1,TWO_ONES=2      AT_LEAST_THREE_ONES=3;

// ************* STRUCTURAL DESCRIPTION  *********** // Instance of a three-state gate that enables output

three_state t1(ungated_detect,output_enable, detect);

// *****************  ALWAYS BLOCK  **************** 

// always block infers flip-flops to hold the state of 

// the FSM.

always @ (posedge clock) begin

   cs = ns;

end

// ************* FUNCTIONAL DESCRIPTION ************

function detect_logic;

   input [1:0] cs; 

   input signal;

   begin

      detect_logic = 0; // default value

      if ( signal == 0 ) // bit is zero

          ns = NO_ONES;

      else             // bit is one,increment state

         case (cs)

            NO_ONES: ns = ONE_ONE;

            ONE_ONE: ns = TWO_ONES;

            TWO_ONES, AT_LEAST_THREE_ONES:

               begin

                  ns = AT_LEAST_THREE_ONES;

                  detect_logic = 1;

               end

         endcase

   end

endfunction

// **************  assign STATEMENT  **************

assign ungated_detect = detect_logic( cs, signal );

endmodule

To successfully synthesize a structural or functional HDL description, the description must conform to the three elements of Verilog synthesis.

• Design methodology
  
  Design methodology refers to the synthesis design process described in the “Foundation Express with Verilog HDL” chapter that uses Foundation Express and a Verilog HDL Simulator.
  
  
• Description style
  
  Use the HDL design and coding style that makes the best use of the synthesis process to obtain high quality results from Foundation Express. See the “Writing Circuit Descriptions” chapter.
  
  
• Language constructs
  
  The third component of the Verilog synthesis policy is the set of Verilog constructs that describes your design, determines its architecture, and gives consistently good results.
  
  Foundation Express uses HDL constructs that maximize coding flexibility while producing consistently good results. Although Foundation Express can read the entire Verilog language, a few HDL constructs cannot be synthesized. These constructs are unsupported, because they cannot be realized in logic. For example, you cannot use simulation time as a trigger, because time is an element of the simulation process and cannot be realized. See the “Unsupported Verilog Language Constructs” section of the “Verilog Syntax” chapter for unsupported Verilog constructs.