Register Selection

The placement of registers and the clocking scheme are important architectural decisions. There are two ways to define registers in your Verilog description; instantiating or inferring registers. Each method has specific advantages and disadvantages.

Register Instantiation

You can directly instantiate registers into a Verilog description, selecting from any element in your FPGA or CPLD library. (Clocking schemes can be arbitrarily complex.) You can choose between a flip-flop or a latch-based architecture. The main disadvantages to this approach follow.

• The Verilog description is specific to a given technology, because you choose structural elements from that technology library. However, you can isolate that portion of your design with directly instantiated registers as a separate component (module), and, then, connect it to the rest of the design.
  
  
• The description is more difficult to write.
  
  

Register Inference

You can use some Verilog constructs to direct Foundation Express to infer registers from the description. This method allows Foundation Express to select the type of component inferred, based on constraints. Therefore, if you need a specific component, you should instantiate registers, instead of inferring them. However, some types of registers and latches cannot be inferred.

The following advantages of inferring registers directly counter the disadvantages of instantiating registers.

• Inferring registers is technology independent.
  
  
• With register inference, the Verilog description is much easier to write.
  
  See the “Register Inference” section of the “Register and Three-State Inference” chapter for a discussion of latch and register inference.