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Foundation Express uses lexical conventions that are nearly identical to those of the Verilog language. The types of lexical tokens that Foundation Express uses are described in the following subsections.
White space separates words in the input description and can contain spaces, tabs, new lines, and form feeds. You can place white space anywhere in the description. Foundation Express ignores white space.
You can enter comments anywhere in a Verilog description in two forms.
Note: You cannot nest comments.
You can declare numbers in several different radices and bit-widths. A radix is the base number on which a numbering system is built. For example, the binary numbering system has a radix of 2, octal has a radix of 8, and decimal has a radix of 10.
You can use these three number formats.
The radix determines which symbols you can include in the number. Constants declared this way are assumed to be 32-bit numbers. Any of these numbers can include underscores ( _ ). The underscores improve readability and do not affect the value of the number. The table below summarizes the available radices and valid characters for the number.
| Name | Character Prefix | Valid Characters |
|---|---|---|
| binary | 'b | 0 1 x X z Z _ ? |
| octal | 'o | 0-7 x X z Z _ ? |
| decimal | 'd | 0-9 _ |
| hexadecimal | 'h | 0-9 a-f A-F x X z Z _ ? |
The following are examples of valid Verilog number declarations.
391 // 32-bit decimal number
'h3a13 // 32-bit hexadecimal number
10'o1567 // 10-bit octal number
3'b010 // 3-bit binary number
4'd9 // 4-bit decimal number
40'hFF_FFFF_FFFF // 40-bit hexadecimal number
2'bxx // 2-bits don't care
3'bzzz // 3-bits high-impedance
Identifiers are user-defined words for variables, function names, module names, and instance names. Identifiers can be composed of letters, digits, and the underscore character ( _ ). The first character of an identifier cannot be a number. Identifiers can be any length. Identifiers are case-sensitive, and all characters are significant.
An identifier that contains special characters, begins with numbers, or has the same name as a keyword can be specified as an escaped identifier. An escaped identifier starts with the backslash character (\) followed by a sequence of characters, followed by white space.
The following are sample escaped identifiers.
\a+b \3state
\module \(a&b)|c
The Verilog language supports the concept of hierarchical names, which can be used to access variables of submodules directly from a higher-level module. Foundation Express partially supports hierarchical names. (For more information, see “Unsupported Verilog Language Constructs” section of this chapter.)
Operators are one-character or two-character sequences that perform operations on variables. Some examples of operators are +, ~^, <=, and >>. Operators are described in detail in the “Operators” section of the “Expressions” chapter.
Macro substitution assigns a string of text to a macro variable. The string of text is inserted into the code where the macro is encountered. The definition begins with the back quotation mark (`), followed by the keyword define, followed by the name of the macro variable. All text from the macro variable until the end of the line is assigned to the macro variable.
You can declare and use macro variables anywhere in the description. The definitions can carry across several files that are read into Foundation Express at the same time. To make a macro substitution, type a back quotation mark (`) followed by the macro variable name.
Some sample macro variable declarations are shown in the following example.
`define highbits 31:29
`define bitlist {first, second, third}
wire [31:0] bus;
`bitlist = bus[`highbits];
Text macros are not supported when used with sized constants, as shown in the following example.
`define SIZE 4
module test (in,out);
output [3:0] out;
input [3:0] in;
assign out = 'SIZE'b0101; //text macro from `define //statement cannot be used with a sized constant
endmodule
The include construct in Verilog is similar to the #include directive in C. You can use this construct to include Verilog code, such as type declarations and functions, from one module into another module. The following example shows an application of the include construct.
Contents of file1.v
`define WORDSIZE 8
function [WORDSIZE-1:0] fastadder;
.
.
endfunction
Contents of secondfile
module secondfile (in1,in2,out)
`include “file1.v”
wire [WORDSIZE-1:0] temp;
assign temp = fastadder (in1,in2);
.
.
endmodule
Included files can include other files, up to 24 levels of nesting. You cannot use the include construct recursively.
Simulation directives refer to special commands that affect the operation of the Verilog HDL Simulator. You can include these directives in your design description, because Foundation Express parses and ignores them.
`accelerate
`celldefine
`default_nettype
`endcelldefine
`endprotect
`expand_vectornets
`noaccelerate
`noexpand_vectornets
`noremove_netnames
`nounconnected_drive
`protect
`remove_netnames
`resetall`timescale
`unconnected_drive
Verilog system functions are implemented by the Verilog HDL simulators to generate input or output during simulation. Their names start with a dollar sign ($). Foundation Express parses and ignores Verilog system functions.