Chapter 7

Foundation Express Directives

Specific aspects of the synthesis process can be controlled by special comments in the Verilog source code called Foundation Express directives. Because these directives are just a special case of regular comments, they are ignored by the Verilog HDL Simulator and do not affect simulation.

Foundation Express directives and their effect on translation are described in the following sections of this chapter.

• “Notation for Foundation Express Directives”
  
  
• “translate_off and translate_on Directives”
  
  
• “parallel_case Directive”
  
  
• “full_case Directive”
  
  
• “state_vector Directive”
  
  
• “enum Directive”
  
  
• “Component Implication”