Foundation
Series User
Guide

Preface

About the Manual

This Foundation Series User Guide provides a detailed description of the Foundation^™ design methodologies, design entry tools, simulation (both functional and timing simulation). Information on synthesis is included for Express users.The manual also briefly describes the Xilinx design implementation tools. Detailed descriptions of the design implementation tools can be found in the two DynaText^® online documents, Design Manager/Flow Engine Reference/User Guide and Development System Reference Guide.

Before using this manual, you should be familiar with the operations that are common to all Xilinx software tools: how to bring up the system, select a tool for use, specify operations, and manage design data. These topics are covered in the Foundation Series Quick Start Guide 1.5. Consult the Verilog Reference Guide and the VHDL Reference Guide for detailed information on using Verilog and VHDL with Foundation Express.

You must consult The Programmable Logic Data Book for device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging. The Programmable Logic Data Book is available in hard copy and on the Xilinx web site (http://www.xilinx.com). See http://www.xilinx.com/partinfo/databook.htm for the current version of this book.

For specific design issues or problems, use the Answers Search function on the world-wide web (http://www.xilinx.com/support/searchtd.htm) to access the following.

• Answers Database: current listing of solution records for the Xilinx software tools
  
  
• Applications Notes: descriptions of device-specific design techniques and approaches
  
  
• Data Sheets: pages from The Programmable Logic Data Book
  
  
• XCELL Journal: quarterly journals for Xilinx programmable logic users
  
  
• Expert Journals: the latest news, design tips, and patch information on the Xilinx design environment
  
  

If you cannot access the Web, you can install and access the Foundation Series Answers book with the DynaText online browser in the same manner as the Xilinx book collection. The Answers book includes information in the Answers Database at the time of this release.

Foundation Series User Guide Contents

This guide covers the following topics:

• Chapter 1, “Introduction,” lists supported architectures, platforms, and features. It also lists the available documentation and tutorials to help you get started with Foundation.
  
  
• Chapter 2, “Project Toolset,” explains the two F1.5 project types - Schematic Flow projects and HDL Flow projects - and how to access the various Foundation design tools from the Project Manager. It briefly describes each tool and its function.
  
  
• Chapter 3, “Design Methodologies - Schematic Flow,” describes various design methodologies for top-level schematic designs and state machine designs in Schematic Flow projects.
  
  
• Chapter 4, “Schematic Design Entry,” explains how to manage your schematic designs and how to create hierarchical schematic designs.
  
  
• Chapter 5, “Design Methodologies - HDL Flow,” describes various design methodologies for HDL, schematic, and state machine designs in HDL Flow projects.
  
  
• Chapter 6, “HDL Design Entry and Synthesis,” describes how to create top-level HDL designs, explains how to manage large designs, and discusses advanced design techniques.
  
  
• Chapter 7, “State Machine Designs,” explains the basic operations for creating state machine designs.
  
  
• Chapter 8, “LogiBLOX,” explains how to create LogiBLOX^™ modules and how to use them in schematic and HDL designs.
  
  
• Chapter 9, “Functional Simulation,” describes the basic functional simulation process.
  
  
• Chapter 10, “Design Implementation,” briefly describes how to implement your design with the Xilinx Implementation Tools. The chapter also describes how to select various design options in the Implementation Options dialog box and describes the Implementation reports.
  
  
• Chapter 11, “Verification and Programming,” explains how to generate a timing-annotated netlist, how to perform a static timing analysis, and describes the basic timing simulation process. An overview of the device download tools is also included.
  
  
• Appendix A, “Glossary,” defines some of the commonly used terms in this manual.
  
  
• Appendix B, “Foundation Constraints,” discusses some of the more common constraints you can apply to your design to control the timing and layout of a Xilinx FPGA or CPLD. It describes how to use constraints at each stage of design processing.
  
  
• Appendix C, “Instantiated Components,” lists the components most frequently instantiated in synthesis designs.
  
  
• Appendix D, “File Processing Overview,” contains diagrams of the file manipulations for FPGAs and CPLDs during the design process.
  
  

Conventions

Typographical

This manual uses the following conventions. An example illustrates each convention.

• Courier font indicates messages, prompts, and program files that the system displays.
  
  speed grade: -100
  
  
• Courier bold indicates literal commands that you enter in a syntactical statement. However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0].
  
  rpt_del_net=
  
  Courier bold also indicates commands that you select from a menu or buttons that you click in dialog boxes.
  
  File Open
  Click OK
  
  
• Italic font denotes the following items.
  
  
  • Variables in a syntax statement for which you must supply values
    
    edif2ngd design_name
    
    
  • References to other manuals
    
    See the Development System Reference Guide for more information.
    
    
  • Emphasis in text
    
    If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
    
    
• Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.
  
  edif2ngd [option_name] design_name
  
  Square brackets also enclose footnotes in tables that are printed out as hardcopy in DynaText^®.
  
  
• Braces “{ }” enclose a list of items from which you must choose one or more.
  
  lowpwr ={on|off}
  
  
• A vertical bar “|” separates items in a list of choices.
  
  lowpwr ={on|off}
  
  
• A vertical ellipsis indicates repetitive material that has been omitted.
  
  IOB #1: Name = QOUT'
  IOB #2: Name = CLKIN'
  .
  .
  .
  
  
• A horizontal ellipsis “. . .” indicates that an item can be repeated one or more times.
  
  allow block block_name loc1 loc2 ... locn;
  
  

Online Document

Xilinx has created several conventions for use within the DynaText online documents.

• Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to open the specified cross-reference.
  
  
• Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to open the specified cross-reference.
  
  
• There are several types of icons.
  
  Iconized figures are identified by the figure icon.
  
  
  
  Iconized tables are identified by the table icon.
  
  
  
  The Copyright icon displays in the upper left corner on the first page of every Xilinx online document.
  
  
  
  The DynaText footnote icon displays next to the footnoted text.
  
  
  
  Double-click on these icons to display figures, tables, copyright information, or footnotes in a separate window.
  
  
• Inline figures display within the text of a document. You can display these figures in a separate window by clicking on the figure.