The Project Manager's Implementation phase button automatically invokes the Flow Engine to process the design. The Flow Engine interface prominently displays the status of each implementation stage as shown in the following figures.
Figure 10.2 Flow Engine - FPGA Processing |  |
Figure 10.3 Flow Engine - CPLD Processing | |
When you process your design, the Flow Engine translates the design file into the Xilinx internal database format (NGD). The Flow Engine then implements your design and generates bitstream data.
Process indicators in the Flow Engine main window show you which of these stages is currently processing. The arrows between each step turn black after the previous step is completed. Underneath each process indicator, a progress bar shows the status of each processing step, whether running, completed, aborted, or failed.
By default, all implementation processing stages are performed. If you want, you can control processing of your design by using the STOP button in the Flow Engine Tool bar to stop processing after a designated stage. Refer to the “Flow Engine Controls” section under the “Additional Implementation Tools” section for more information on additional features of the Flow Engine.
For an overview of the processing and file manipulation performed for FPGAs and CPLDs, refer to the “File Processing Overview” appendix.
The Flow Engine's first step, Translate, merges all of the input netlists. This is accomplished by running NGDBuild. For a complete description of NGDBuild, refer to the “NGDBuild” chapter of the Development System Reference Guide.
The MAP program maps a logical design to a Xilinx FPGA. The input to a mapping program is an NGD file, which contains a logical description of the design in terms of both the hierarchical components used to develop the design and the lower level Xilinx primitives, and any number of NMC (macro library) files, each of which contains the definition of a physical macro. MAP first performs a logical DRC (Design Rule Check) on the design in the NGD file. MAP then maps the logic to the components (logic cells, I/O cells, and other components) in the target Xilinx FPGA. The output design is an NCD (Native Circuit Description) file physically representing the design mapped to the components in the Xilinx FPGA. The NCD file can then be placed and routed.
You can run the Mapper from a GUI (Flow Engine) or command line. For a description of the GUI, see the DynaText online document, Design Manager/Flow Engine Reference/User Guide. For a description of the MAP command and its options, see the DynaText online document, Development System Reference Guide.
After an FPGA design has undergone the necessary translation to bring it into the NCD (Circuit Description) format, it is ready to place and route. This phase is done by PAR (Xilinx's Place and Route program). PAR takes an NCD file, places and routes the design, and produces an NCD file, which is used by the bitstream generator (BitGen). The output NCD file can also act as a guide file when you place and route the design again after you make minor changes to it.
In the Xilinx Development System, PAR places and routes a design using a combination of two methods.
For a complete description of PAR, see the “PAR - Place and Route” chapter in the Development System Reference Guide.
The CPLD Fitter implements designs for the XC9500/XL devices. The Fitter outputs the files listed below.
Programs Accessories Design Manager.For detailed information about implementing CPLD designs, refer to the CPLD Design Techniques and CPLD Flow Tutorial in the Foundation on-line help.
After the design has been completely routed, you must configure the device so that it can execute the desired function. Xilinx's bitstream generation program, BitGen, takes a fully routed NCD (Circuit Description) file as its input and produces a configuration bitstream - a binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA's memory cells, or it can be used to create a PROM file.
For a complete description of BitGen, see the “BitGen” chapter in the Development System Reference Guide. This chapter also explains how to use the command line to run BitGen.
Within the Flow Engine, BitGen runs as part of the Configure process. For details consult the various configuration template options in the “Setting Custom Template Options” section in the “Using the Design Manager” chapter of the Design Manager/Flow Engine Reference/User Guide.
At the end of a successful CPLD implementation, a .jed programming file is created. The JTAG Programmer uses this file to configure XC9500/XL CPLD devices.
