Options Dialog Box
Use the design implementation Options dialog box to set options for implementing a design.
To open this dialog box, do one of the following.
- From the Design Manager, select Design
Implement or, if you want to run place and route passes, Design FPGA Multi-Pass Place & Route. In the dialog box that appears, click the Options button.
- From the Flow Engine, select Setup Options or click the Design Implementation Options toolbar button.
The Options dialog box appears, as shown in the following figure.
NOTEThe Options dialog box differs slightly between FPGAs and CPLDs. The following figure shows the dialog box for FPGAs.
| To implement your design after you have made your option settings, do one of the following.
- If you opened the dialog box from the Design Manager, click the Run button in the Implement or FPGA Multi-Pass Place & Route dialog box.
- If you opened the dialog box from the Flow Engine, select Flow Run or click the Run button in the Flow Engine main window.
Options Dialog Box Options
The following options are available in the Options dialog box.
User Constraints
Specify a user constraints file (UCF) to use for this implementation. Click Browse to open a file selection dialog box in which you can select an existing UCF file. You can specify logic placement and timing requirements in the UCF file.
NOTEWhen initially creating a project, include a user-generated UCF file in the same directory as your input design and the UCF file will appear in this field automatically.
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Program Option Templates
The Program Option Templates field contains the following options.
- Implementation - Drop-down List
Implementation templates control how the software maps, places, routes, and optimizes an FPGA design and how the software fits a CPLD design. Select an implementation template to use from the Implementation drop-down list. All of the implementation templates that you created with the Template Manager command appear when you click on this drop-down list.
- Implementation - Edit Template Button
Click the Edit Template button to the right of the Implementation drop-down list to open the Implementation Template dialog box. The options in this box depend on the target device family. For information on how to use the implementation template options, see one of the following sections.
- Simulation - Drop-down List
Simulation templates control the creation of netlists in terms of the Xilinx primitive set, which allow you to simulate and back-annotate your design. In back-annotation, physical design data is distributed back to the logic design to perform back-end simulation. You can perform front and back-end simulation on both pre- and post-routed designs. Select a simulation template to use from the Simulation drop-down list. All of the simulation templates that you created with the Template Manager command appear when you click on this drop-down list.
- Simulation - Edit Template button
Click the Edit Template button to the right of the Simulation drop-down list to open the Simulation Template dialog box. The options in this dialog box are almost identical across device families. For information on the simulation options, see the “Spartan Simulation Template Dialog Box” section.
- Configuration - Drop-down List (FPGA only)
Configuration templates control the configuration parameters of a device, the startup sequence, and readback capabilities. Select a configuration template to use in this implementation from the Configuration drop-down list. All of the configuration templates that you created with the Template Manager command appear when you click on this drop-down list.
- Configuration - Edit Template button (FPGA only)
Click the Edit Template button to the right of the Configuration drop-down list to open the Configuration Template dialog box. The options in this dialog box depend on the target device family. For information on the configuration options, see one of the following sections.
Optional Targets
The Optional Targets field contains the following options.
- Produce Timing Simulation Data
Select this option to produce timing simulation data. This data is produced after the design is placed and routed for FPGAs and after the design is fitted for CPLDs. See the “Producing Timing Simulation Data” section of the “Using the Design Manager” chapter for more information.
- Produce Configuration Data
Select this option to produce configuration data. This data is produced after design implementation. The configuration data is used to program a device.
